This invention relates to a method of manufacturing a compound semiconductor devices such as a heterojunction bipolar transistor (HBT), a hot electron transistor (HET), a field effect transistor (FET) and an integrated circuit (IC) including these devices.
In manufacturing a compound semiconductor device like an HBT or FET, it is often necessary to prevent undesirable electrical contacts between neighboring devices by a process known as device-to device isolation. This is commonly achieved through etching of the conducting material in the regions between devices or through ion implantation to convert those regions to an insulating state. After device-to-device isolation, each device is surrounded by insulating material like an island. It is also necessary to fabricate electrical connections between the electrodes (e.g. the emitter, base, and collector electrodes of an HBT) of the devices to form functional circuits, as by electroplating or by bonding wires. In order to facilitate alignment of these electrical connections to the electrodes, which can be of very small dimensions, contact pads are typically fabricated contiguous to and at the same time as the electrodes. With these pads, an undesirable, parasitic capacitance is associated. This parasitic capacitance is generally minimized by fabricating the pads on the insulating regions between devices. Therefore, a typical device fabrication sequence consists of first device-to-device isolation, next electrode formation, including etching to expose various device layers (e.g. base exposure etch or FET gate recess etch), and finally interelectrode connection formation. However, although these exposure etches must be precisely controlled for optimal device performance, it is widely understood that etching uniformity decreases when performed on isolated devices, particularly when the regions to be etched have various sizes. This problem is sometimes solved in the case of common source FET applications by using a partial isolation process which isolates all drain areas, but leaves the source areas in electrical contact.
According to the conventional isolation method, there is a trade-off between parasitic capacitance and etching uniformity. The etching uniformity may be increased at the expense of increased parasitic capacitance, or the parasitic capacitance may be reduced.
In addition, the etching uniformity may be realized in the conventional partial isolation method. However, the application of this method is restricted to specific circuits, since all devices are in an electric contact after the fabrication. For example, the application of the method is mainly restricted to the common source FET circuit in the fabrication of the FET.